Packaged semiconductor devices are currently handled and shipped in a variety of media. The predominant shipping medium for devices with a large numbers of leads or fragile leads is a tray 10, illustrated in FIG. 1, composed of a support frame 11 and a matrix of cells 12. Each cell 12 is intended to contain one semiconductor device. In a typical handling procedure, shipping trays containing devices within the cells are stacked on top of each other with the top tray being empty and serving only as a lid. Many current configurations of semiconductor device packages are commonly handled and shipped in matrix trays. Examples of these packages commonly processed and shipped in trays include gull-wing-leaded quad flat package (QFP), pin grid array (PGA), ball/bump grid array (BGA), column grid array (CGA), pad array carrier (PAC), plastic leaded chip carrier (PLCC), and thin small outline package (TSOP).
Although many semiconductor devices are shipped in trays, numerous handling problems exist with the use of currently available trays. A primary problem with existing trays is inadequate protection of the semiconductor devices during normal processing/handling and in shipping. Another major problem is the inability to invert the trays and still retain the devices for processing. Other significant problems include poor mating between trays causing device damage during tray stacking, lack of adequate segmentation between cells which allows one device to migrate to an adjacent cell and damage the neighboring device, and insufficient device retention features in each cell allowing devices to break or override the retention features.
Existing trays place significant constraints on the design and performance of the lead forming, handling and test equipment used to manufacture semiconductor devices. The trays place similar constraints on the equipment used to mount semiconductor devices to circuit boards. The known individual tray cell configurations often do not provide sufficient location precision of the semiconductor device contained therein relative to the tray edges. Hence, accurate placement of the device into a test socket or onto a circuit board is not possible without first placing the device on a mechanical or optical centering mechanism. Additionally, the existing cell designs often shroud or obscure the device leads in such a manner that automated in-tray inspection is impractical. Furthermore, most current trays cannot be inverted without damaging the semiconductor devices contained therein. In addition, current trays have no provision for in-tray electrical verification or burn-in of the semiconductor devices.
One current solution to the poor mating problem between stacked trays is a tongue and groove style of interlock between tray cells along the long axis of a TSOP tray. This longitudinal interlock is only a partial solution because it simply provides longitudinal alignment and registration sufficient for TSOP packages which have leads on only two sides of the package body. The interlocking is inadequate for the semiconductor device packages which have leads on all four sides. Furthermore, this interlocking solution does not allow for inversion of the trays without damaging the devices contained therein. Several tray manufacturers offer trays which allow a primitive form of inversion. One design has no features for retaining the device in the cell when inverted so the inversion is essentially a one-time operation. Another design has retaining features that do not guide the device into correct alignment with the retaining features; hence it is very difficult to place the device in the cell unless the device is already precisely aligned with the cell. Neither design provides sufficient guiding or locating features to permit unstacking and restacking of the trays while inverted without potentially damaging the device contained therein. These known trays have no provision for facilitating in-tray electrical verification, burn-in or inspection.
Some variants of the QFP, PGA, BGA, PLCC, and TSOP semiconductor device packages have also been shipped in other shipping media, such as tubes and tape and reel. Difficulties encountered in using the tubes include package lead deformation from devices colliding with each other and the tube, cracking and chipping of the package body, cosmetic and functional abrasions on the package from contact with the tube, contamination of the packages with particulates from the tube, and package damage during insertion and removal from the tube. Problems with the tape and reel shipping medium include damage to the semiconductor device leads during insertion and removal of the device from the tape pocket, adhesion of the device package body to the cover tape, damage to the device leads during reeling and de-reeling, and damage to the device leads due to crushing of the pockets or devices overriding the retaining features of the pocket.
Another disadvantage associated with both the tube and tape and reel shipping media is that electrical verification of the devices is not possible once the devices are placed in the tubes or the tape. Furthermore, visual inspection of the devices in the tubes is generally not possible except cursory verification of gross features. Visual inspection of the top surface of the devices is possible with the tape and reel medium, but side and bottom visual inspections are not possible in the tape. Additionally, many semiconductor device package types simply cannot be shipped in tubes or tape and reel. Hence, the preferred shipping medium for the many semiconductor device package types is the tray. Thus, it is desirable to have a tray which addresses all of the aforementioned problems and limitations found in the current trays.